Microprocessor Design/Computer Architecture - Wikibooks, open books for an open world. Von Neumann Architecture. To reprogram a computer meant changing the hardware switches manually, that took a long time with potential errors. Computer memory was only used for storing data. John von Neumann suggested that data and programs should be stored together in memory. This is now called Von Neumann architecture. Programs are fetched from memory for execution by a central unit that we call the CPU.
Basically programs and data are represented in memory in the same way. The program is just data encoded with special meaning. The main criticism of this approach is, that security problems can arise when instructions can be manipulated as if they were data, and vice- versa. A Von Neumann microprocessor is a processor that follows this pattern: Fetch. An instruction and the necessary data are obtained from memory.
Decode. The instruction and data are separated, and the components and pathways required to execute the instruction are activated. Execute. The instruction is performed, the data is manipulated, and the results are stored. This pattern is typically implemented by separating the task into two components, the control, and the datapath.
Lec 1 - Introduction to Microprocessors & Microcontrollers. Architecture and Organization of 8085 - Duration.
Components of a Microprocessor. Fagg: Embedded Real-Time Systems: Microcontrollers 2 Components of a Microprocessor. Atmel Mega2560 Architecture. Fagg: Embedded Real-Time Systems: Microcontrollers 20. Microprocessor & Programming. Basic knowledge computer architecture and digital electronics is helpful. 2.1 Silent features of 8086 Microprocessor, architecture of 8086. MICROPROCESSOR ARCHITECTURE This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as The policies. ARMARM Microprocessor Basics Microprocessor Basics. ARM Processor Architecture (ARM core). ThisisbasiccoreandallcorehaveTDMIThis is basic core and all core have TDMI.
Control. As the data travels to different parts of the datapath, the command signals from the control unit cause the data to be manipulated in specific ways, according to the instruction. The datapath consists of the circuitry for transforming data and for storing temporary data. It contains ALUs capable of transforming data through operations such as addition, subtraction, logical AND, OR, inverting, and shifting. We discuss the control and datapath in far more detail in a later section, Control and Datapath. Harvard Architecture. In a pure Harvard system, the two different memories occupy separate memory modules, and instructions can only be executed from the instruction memory.
Microprocessor Design. This book is intended for advanced readers. A PDF version is available. Microprocessor Basics. Basic Theory; Microprocessors; Computer Architecture; Instruction Set Architectures. Describe the basic operation. Having learned basic concepts with the 8085 microprocessor. Microprocessor Architecture, Programming, and Applications with. The evolution of microprocessor architecture depends upon the changing aspects of technology. As die density and speed increase, memory and program behavior bec.
Many DSPs are modified Harvard architectures, designed to simultaneously access three distinct memory areas: the program instructions, the signal data samples, and the filter coefficients (often called the P, X, and Y memories). In theory, such three- way Harvard architectures can be three times as fast as a Von Neumann architecture that is forced to read the instruction, the data sample, and the filter coefficient, one at a time.
Modern Computers. All information, program instructions, and data are stored in the same RAM areas. However, a modern feature called . Each page of memory can either be instructions or data, but not both.
Modern embedded computers, however, are typically based on a Harvard architecture. Instructions are stored in a different addressable memory block than the data is, and there is no way for the microprocessor to interchange data and instructions. RISC and CISC and DSP. It is a common misunderstanding that RISC systems typically have a small ISA (fewer instructions) but make up for it with faster hardware. RISC system actually have .
It is a common misunderstanding that CISC systems have more instructions, but typically pay a steep performance penalty for the added versatility. CISC systems actually have . MIPS and SPARC are examples of RISC computers. Intel x. 86 is an example of a CISC computer. Some people group stack machines with the RISC machines; others. An instruction to add two numbers together would cause the Control Unit to activate the addition module, for instance. I/O Units. This communication occurs through the I/O ports.
The I/O ports will interface with the system memory (RAM), and also the other peripherals of a computer. Arithmetic Logic Unit. ALUs can typically add, subtract, divide, multiply, and perform logical operations of two numbers (and, or, nor, not, etc). Hopefully it will be obvious which kind of register we are talking about from the context. The most general meaning is a . Since registers outside of a CPU are also outside the scope of the book, this book will only discuss processor registers, which are hardware registers that happen to be inside a CPU. But usually we will refer to a more specific kind of register.
Registers are mentioned in far more detail in a later chapter, Register File. In most processors, there are fewer than 3. The size of the registers defines the size of the computer.
The length of a register is known as the word length of the computer. There are several factors limiting the number of registers, including: It is very convenient for a new CPU to be software- compatible with an old CPU. This requires the new chip to have exactly the same number of programmer- visible registers as the old chip. Doubling the number general- purpose registers requires adding another bit to each instruction that selects a particular register. Each 3- operand instruction (that specify 2 source operands and a destination operand) would expand by 3 bits.
Modern chip manufacturing processes could put a million registers on a chip; that would make each and every 3- operand instruction require 6. Adding more registers adds more wires to the critical path, adding capacitance, which reduces the maximum clock speed of the CPU. Historically, CPUs were designed with few registers, because each additional register increased the cost of the CPU significantly.
But now that modern chip manufacturing can put tens of millions of bits of storage on a single commodity CPU chip, this is less of an issue. Microprocessors typically contain a large number of registers, but only a small number of them are accessible by the programmer. The registers that can be used by the programmer to store arbitrary data, as needed, are called general purpose registers. Registers that cannot be accessed by the programmer directly are known as reserved registers.
The vast majority of these microarchitectural registers are technically not . A designer could choose to design a CPU that had almost no physical registers other than the programmer- visible registers. However, many designers choose to design a CPU with lots of physical registers, using them in ways that make the CPU execute the same given instruction set much faster than a CPU that lacks those registers.
Most CPUs manufactured do not have any cache. Cache is memory that is located on the chip, but that is not considered registers. The cache is used because reading external memory is very slow (compared to the speed of the processor), and reading a local cache is much faster. In modern processors, the cache can take up as much as 5. The following table shows the relationship between different types of memory: smallestlargest. Registerscache. RAMfastestslowest.
Cache typically comes in 2 or 3 . Level 1 (L1) cache is smaller and faster than Level 2 (L2) cache, which is larger and slower. Some chips have Level 3 (L3) cache as well, which is larger still than the L2 cache (although L3 cache is still much faster than external RAM). We discuss cache in far more detail in a later chapter, Cache. Different computers order their multi- byte data words (i.
RAM. Each individual byte in a multi- byte word is still separately addressable. Some computers order their data with the most significant byte of a word in the lowest address, while others order their data with the most significant byte of a word in the highest address.
There is logic behind both approaches, and this was formerly a topic of heated debate. This distinction is known as endianness. Computers that order data with the least significant byte in the lowest address are known as . It is easier for a human (typically a programmer) to view multi- word data dumped to a screen one byte at a time if it is ordered as Big Endian. However it makes more sense to others to store the LS data at the LS address. When using a computer this distinction is typically transparent; that is that the user cannot tell the difference between computers that use the different formats.
However, difficulty arises when different types of computers attempt to communicate with one another over a network. With a big- endian 6. K sort of machine. The little- endian x. High- level software (should) format packets of data to be transmitted over the network in Network Byte Order. High- level software (should) be written as . Software that is not .
They always read and write complete aligned words, and don't have any hardware for dealing with individual bytes. Systems build on top of such computers often *do* have a particular endianness - - but that endianness is written into the software, and can be switched by re- compiling for the opposite endianness. A stack is a block of memory that is used as a scratchpad area. The stack is a sequential set of memory locations that is set to act like a LIFO (last in, first out) buffer. Data is added to the top of the stack in a . Most computer architectures include at least a register that is usually reserved for the stack pointer. Some microprocessors include a small hardware stack built into the CPU, independent from the rest of the RAM.
Some people claim that a processor must have a hardware stack in order to run C programs. Some architectures (such as the ARM, the Freescale RS0. A separate instruction near the beginning of the subroutine pushes the contents of the link register to a stack in main memory, to free up the link register so that subroutine can then recursively call other subroutines. Some architectures (such as the 6.